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SOURCE Cadence Design Systems, Inc.
- Hitachi chooses Tempus Timing Signoff Solution to tape out their latest giga-scale design at the 28nm process node.
- Hitachi also used Tempus physically aware Timing Signoff Optimization (TSO) to significantly reduce design closure phase, as well as QRC to improve overall throughput for multi-corner parasitic extraction.
- To achieve the best correlation to SPICE, Hitachi utilized ECSM timing models for their standard cell library.
SAN JOSE, Calif., July 7, 2014 /PRNewswire/ -- Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that Hitachi has taped out its latest giga-scale design using the Cadence Tempus™ Timing Signoff Solution. Hitachi also utilized Tempus Timing Signoff Optimization (TSO), resulting in a reduction of their overall closure time to just 3 weeks down from almost 2 months. This represents a significant improvement in ECO iterations versus their previous solution. The Tempus solution's advanced capabilities were able to analyze over 50M cells flat in the design, an analysis that normally requires a hierarchical signoff flow. Hierarchical strategies were used extensively during the implementation phase; however, flat analysis was needed at signoff to ensure the best accuracy.
The Tempus solution is the lead tool in a new class of massively parallel timing signoff tools and capabilities, which enable customers to shrink timing signoff closure and analysis turnaround time to a minimum. In addition to faster time-to-tapeout, designs are produced with less pessimism, area and power consumption through physically aware and path-based analysis optimization. By combining the massively parallelized capabilities of Tempus and QRC together and leveraging native database formats, Hitachi was able to improve time-to-tapeout well beyond those of existing mixed tool flows.
"The size and complexity characteristics of our latest design required a timing solution that could handle 50M cells quickly and efficiently," said Yuko Ito, director for Design Engineering First Department, Platform Advanced Engineering Operation, Information & Telecommunication Systems Company, Hitachi, Ltd. "The Tempus solution met our turnaround time challenge while ensuring the highest level of correlation to SPICE."
In addition, Toru Hiyama, general manager for Platform Advanced Engineering Operation, Information & Telecommunication Systems Company, Hitachi, Ltd. remarked, "The Tempus Timing Signoff Solution and QRC were the right timing platform to address our signoff analysis and closure needs. With strong support from Cadence, we expect continued success in taping-out leading-edge designs at 28nm and beyond."
"We have worked very closely with Hitachi to ensure that the Tempus solution fulfills the requirements of its next generation of product design cycles," said Anirudh Devgan, senior vice president of the Digital and Signoff Group (DSG) at Cadence. "The Tempus solution is the first innovation in a platform of signoff tools that brings a scalable and complete signoff solution to our customers now and at smaller process nodes."
To learn more about Tempus Timing Signoff Solution capabilities, please visit http://www.cadence.com/products/mfg/tempus/pages/default.aspx.
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence® software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available here.
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